Digital Logic and Gateware experimental

Digital Logic and Gateware From the transistor to a working processor: logic gates, Boolean and multi-valued logic, and the full FPGA gateware flow. Gates and Boolean logic. Gates and Boolean logic. Build combinational circuits.. Explain why NAND and NOR are universal gates and identify the canonical sum-of-products form of a given truth table.. Transistors to gates, Boolean algebra, Multi-valued logic, Minimisation Transistors to gates Every digital circuit is built from switches. A metal-oxide-semiconductor field-effect transistor (MOSFET) acts as a voltage-controlled switch: an n-channel MOSFET (NMOS) transistor conducts when its gate is high, a p-channel MOSFET (PMOS) transistor conducts when its gate is low. Pairing a PMOS pull-up network with an NMOS pull-down network gives complementary metal-oxide-semiconductor logic, universally abbreviated CMOS (CMOS), where exactly one network conducts for any input combination, so the output is always driven to a solid 0 or 1 and the gate draws almost no static current. The simplest CMOS gate is the inverter: one PMOS from the positive supply rail (VDD) to the output, one NMOS from the output to ground, both driven by the same input. Stacking and combining pull-up/pull-down networks yields the NAND gate (NAND), which computes NOT AND, the NOR gate (NOR), which computes NOT OR, plain AND, OR, exclusive OR (XOR), and buffers. NAND and NOR are called universal gates because either one alone, wired in different combinations, can implement any Boolean function; this is why standard-cell libraries are built almost entirely from NAND and NOR cells rather than AND and OR directly. Boolean algebra Boolean algebra is the algebra of variables that take only the values 0 and 1, combined with AND (·), OR (+), and NOT (‾). It obeys familiar laws (commutativity, associativity, distributivity) plus laws with no arithmetic analogue: idempotence (A·A = A), absorption (A + A·B = A), and complementation (A·A' = 0, A + A' = 1). De Morgan's theorems, (A·B)' = A' + B' and (A+B)' = A'·B', let you push inversions through a circuit and convert between AND/OR and NAND/NOR forms, which is essential for mapping a design onto a NAND-only cell library. Any Boolean function can be written as a sum-of-products expression (SOP), an OR of AND terms, one per row where the function is 1, or as a product-of-sums expression (POS), an AND of OR terms. These canonical forms are the starting point for simplification and for direct truth-table-to-gate translation. Multi-valued logic Real simulators cannot represent circuits with only 0 and 1. IEEE 1164 std_logic defines nine values, but the practical ones are '0', '1', 'Z' (high-impedance, used for tri-state buses and undriven nets), 'X' (unknown/contention, e.g., two drivers fighting), and 'U' (uninitialised). A net reading 'X' after reset is a red flag: it usually means a register was never initialised or a bus has no default driver. 'Z' is not a value a gate can compute with: it only exists where a tri-state driver is disabled, letting another driver own the wire. Minimisation Unsimplified SOP expressions waste gates. Karnaugh maps (K-maps) simplify functions of up to about six variables by arranging minterms so that adjacent cells differ in one bit; grouping adjacent 1s into the largest possible power-of-two rectangles (1, 2, 4, 8 cells) yields prime implicants, and picking a minimal set of groups that covers every 1 gives a minimal SOP. Don't-care cells (marked X) may be grouped as either 0 or 1, whichever gives a bigger, cheaper group. For more variables, the tabular Quine-McCluskey method automates the same reasoning and is what real synthesis tools generalise into multi-level logic optimisation. Power and noise margins A CMOS gate dissipates power in two distinct ways: static power, drawn even when the output is not switching, which is nominally close to zero because exactly one of the pull-up or pull-down network is always off; and dynamic power, drawn while charging and discharging the output's parasitic capacitance every time it switches, which scales with switching frequency, supply voltage squared, and load capacitance. A noise margin is the amount by which a driving gate's worst-case output voltage differs from the receiving gate's input threshold; a design with thin noise margins is more susceptible to crosstalk and supply noise flipping a logic level it should not, which is why standard-cell libraries publish guaranteed high and low noise margins for every cell and why timing sign-off checks them alongside delay. Fan-out and propagation delay Fan-out is the number of gate inputs a single output drives; each additional input adds capacitance the driving gate must charge or discharge, so propagation delay grows with fan-out rather than staying constant. A cell library specifies a maximum fan-out per drive strength, and a design that exceeds it either needs a stronger buffer inserted or the load split across more than one driver. This is why a synthesis tool reports fan-out and load capacitance alongside delay: a logically correct netlist can still fail to meet a clock-frequency target purely because a signal fans out to too many downstream gates without adequate buffering. Related CCI capabilities Computer Architecture (Course): (https://www.cambridgecyberinternational.com/en/insights/academy/computer-architecture/). Optics Primer Series (Course): (https://www.cambridgecyberinternational.com/en/insights/academy/optics/). Maths Refresher Series, Finance (Course): (https://www.cambridgecyberinternational.com/en/insights/academy/maths-finance/). System Dynamics (Course): (https://www.cambridgecyberinternational.com/en/insights/academy/system-dynamics/). CCI Lab: Run it, build with it, read the thinking, reuse the data. (https://www.cambridgecyberinternational.com/en/insights/lab/) Sequential logic. Sequential logic. Design circuits with state.. Describe the difference between a Moore and a Mealy machine and analyse a timing diagram to compute the minimum clock period a synchronous path allows.. Latches and flip-flops, Registers, Finite state machines, Timing Latches and flip-flops Combinational logic has no memory: its output depends only on its current inputs. Adding feedback creates memory. The simplest latch is the set-reset latch, commonly abbreviated the SR latch (SR), built from two cross-coupled NOR (NOR) gates or, equivalently, two cross-coupled NAND (NAND) gates: setting S=1 forces the output Q to 1, R=1 forces it to 0, and S=R=0 holds whichever state it was last in. The gated D-latch adds an enable input so the latch is transparent (Q follows D) while enable is high and holds Q when enable goes low. Latches are level-sensitive, which makes timing analysis hard in large designs, so most synchronous logic instead uses edge-triggered D flip-flops, built internally as two latches in a master-slave configuration. A D flip-flop samples D at the active clock edge (rising or falling) and holds that value until the next active edge, regardless of what D does in between. This edge-triggered behaviour is what makes synchronous design tractable: every flip-flop in the system updates at the same well-defined instants. Registers A register is simply a bank of D flip-flops sharing a common clock, used to store a multi-bit word for one clock cycle at a time. Registers commonly add a synchronous or asynchronous reset (to force a known value at startup) and a clock-enable (to hold the current value even though the clock keeps ticking, useful for stalling a pipeline). Shift registers chain flip-flops so each stage's output feeds the next stage's input, useful for serial-to-parallel conversion and for building simple delay lines or linear-feedback shift registers (LFSRs). Finite state machines A finite state machine (FSM) pairs a state register with combinational next-state logic and output logic. In a Moore machine, outputs depend only on the current state, so outputs are glitch-free and change only at clock edges. In a Mealy machine, outputs depend on both state and current inputs, which can react one cycle sooner but risks combinational glitches propagating to the output. Designing an FSM means drawing a state diagram, encoding each state as a bit pattern (binary, one-hot, or Gray), writing the next-state function for every state/input pair, and deriving the output function. One-hot encoding uses more flip-flops but simpler, faster next-state logic: a common trade-off on a field-programmable gate array (FPGA) since flip-flops are cheap there. Timing Every flip-flop has a setup time (the interval before the clock edge during which D must be stable) and a hold time (the interval after the edge during which D must remain stable). Violating either risks metastability: the flip-flop's output hovers at an invalid voltage before resolving unpredictably to 0 or 1, and if that resolution takes too long it can propagate a glitch downstream. The maximum clock frequency of a synchronous path is bounded by clock period ≥ clock-to-Q delay + combinational logic delay + setup time. Signals crossing from one clock domain to another are especially prone to metastability and require synchroniser flip-flop chains (typically two or three stages) to reduce the failure probability to acceptable levels. Reset strategies A synchronous reset only takes effect on an active clock edge, which keeps every register's reset timing aligned with the rest of the synchronous logic and avoids adding a large asynchronous fan-out net, but it cannot force a known state if the clock is not toggling. An asynchronous reset takes effect immediately regardless of the clock, which is essential for guaranteeing a defined power-up state, but the reset's release, called reset de-assertion, must itself be synchronised to the clock edge; releasing an asynchronous reset at an arbitrary instant can violate a flip-flop's recovery time and trigger the same metastability risk this module's timing material describes for ordinary data inputs. Most production designs use an asynchronous assertion with a synchronous de-assertion for exactly this reason. Verification of sequential designs A state machine's correctness is not fully captured by simulating a handful of directed test cases, since a bug may only appear after a specific, rare sequence of inputs reaches an unanticipated state. Formal verification tools instead prove properties about every reachable state exhaustively, for example that a particular illegal state combination can never occur, or that every state in the diagram is reachable from reset, catching classes of sequential bugs that simulation alone would need an impractically long random test to stumble onto. Assertion-based verification embeds these properties directly in the hardware description language source, alongside the design, so that a simulator or a formal tool checks them automatically as the design changes rather than relying on a separate, easily stale test plan. Related CCI capabilities Computer Architecture (Course): (https://www.cambridgecyberinternational.com/en/insights/academy/computer-architecture/). Optics Primer Series (Course): (https://www.cambridgecyberinternational.com/en/insights/academy/optics/). Maths Refresher Series, Finance (Course): (https://www.cambridgecyberinternational.com/en/insights/academy/maths-finance/). System Dynamics (Course): (https://www.cambridgecyberinternational.com/en/insights/academy/system-dynamics/). CCI Lab: Run it, build with it, read the thinking, reuse the data. (https://www.cambridgecyberinternational.com/en/insights/lab/) Datapath and a tiny CPU. Datapath and a tiny CPU. Assemble a datapath.. State the two's-complement rule for subtraction and evaluate a ripple-carry adder's worst-case delay as a function of operand width.. ALU, Registers and buses, Control, A minimal processor ALU The arithmetic logic unit (ALU) computes a function of two operands selected by an opcode: typically addition (ADD), subtraction (SUB), bitwise AND, bitwise OR, exclusive OR (XOR), and a shift or comparison operation. Addition is built from a chain of full adders, each taking two bits and a carry-in and producing a sum bit and carry-out; a ripple-carry adder chains N full adders for an N-bit sum but its worst-case delay grows with N because the carry must propagate through every stage. Subtraction reuses the adder by two's-complement negation: A − B = A + (~B) + 1, so an XOR gate on each B input (controlled by the subtract signal) plus forcing carry-in to 1 turns an adder into an adder/subtractor. The ALU also produces status flags: Zero (result is all zeros), Carry (carry-out of the most significant bit (MSB), indicating unsigned overflow), Negative (the sign bit, i.e. the MSB, of a signed result), and Overflow (signed overflow, computed from the carry into and out of the MSB disagreeing). A multiplexer selects which operation's result reaches the ALU output based on the opcode. Registers and buses A datapath moves data between a register file, the ALU, and memory over shared buses. Because a bus can only be driven by one source at a time, sources are connected through tri-state buffers or, more commonly in modern designs, through multiplexers that select exactly one input per cycle: multiplexer-based buses avoid the 'X' contention states that tri-state buses can produce if two enables are asserted simultaneously. A register file is a small array of registers with one or more read ports (combinational, address-in/data-out) and a write port (synchronous, gated by a write-enable and clocked on the active edge), enabling a datapath to read two source registers and write one destination register in the same cycle. Control The control unit turns each instruction's opcode into the set of control signals that steer the datapath for that instruction: which registers to read, what ALU operation to perform, whether to read or write memory, and what to write back. A hardwired controller implements this as combinational logic or, for multi-cycle designs, a small finite state machine (FSM), directly from the opcode bits. A microcoded controller instead stores, for each opcode, a sequence of control-word 'microinstructions' in a small read-only memory (ROM), trading gate count for flexibility and easier debugging: the classic trade-off between speed (hardwired) and design simplicity (microcode). A minimal processor A minimal single-cycle CPU fetches an instruction from memory at the program counter (PC), decodes it into register addresses and an opcode, reads the register file, executes the operation in the ALU, optionally accesses data memory, writes back a result, and computes the next PC (PC+4, or a branch target if a branch condition is met), all within one clock cycle. Even a three-instruction subset (for example, add, load-word, and branch-if-zero) exercises every major datapath block: the fetch/PC logic, the register file, the ALU, the memory interface, and the control logic that ties them together. This is exactly the skeleton that real reduced instruction set computer (RISC) processors, such as RISC-V, extend with pipelining, more instructions, and hazard handling. Multiplication and division Multiplication and division are not built into the minimal single-cycle ALU described above; they need dedicated datapath extensions because a naive combinational multiplier's delay grows much faster than an adder's as operand width increases. A simple sequential multiplier uses a shift-and-add algorithm, computing one partial product per cycle over as many cycles as there are bits, trading latency for a far smaller circuit than a fully combinational array multiplier. Division follows an analogous shift-and-subtract pattern and is markedly harder to make fast, which is one reason many small processor cores omit a hardware divider entirely and instead trap to a software routine when a division instruction is decoded. Pipelining preview Splitting the single-cycle datapath in this module into pipeline stages, for example separate fetch, decode, execute, memory, and write-back stages each running in its own clock cycle, lets a processor start a new instruction every cycle instead of waiting for the previous instruction to traverse the entire datapath first. The trade-off is hazards: a later stage may need a value a still-in-flight earlier instruction has not yet produced, or a branch decided late in the pipeline may invalidate instructions already fetched behind it. Resolving these hazards, through forwarding, stalling, or branch prediction, is what turns this module's single-cycle skeleton into the pipelined designs real processors ship with. Related CCI capabilities Computer Architecture (Course): (https://www.cambridgecyberinternational.com/en/insights/academy/computer-architecture/). Optics Primer Series (Course): (https://www.cambridgecyberinternational.com/en/insights/academy/optics/). Maths Refresher Series, Finance (Course): (https://www.cambridgecyberinternational.com/en/insights/academy/maths-finance/). System Dynamics (Course): (https://www.cambridgecyberinternational.com/en/insights/academy/system-dynamics/). CCI Lab: Run it, build with it, read the thinking, reuse the data. (https://www.cambridgecyberinternational.com/en/insights/lab/) The FPGA flow. The FPGA flow. Follow synthesis to a device.. Explain why an incomplete combinational branch in an HDL infers an unintended latch and justify the use of a self-checking testbench over manual waveform inspection.. HDL, Synthesis, Place and route, Testbenches HDL Hardware description languages (HDLs) such as Verilog, SystemVerilog, and Very High Speed Integrated Circuit Hardware Description Language (VHDL) describe circuits, not sequential programs, even though their syntax resembles software. Combinational logic is typically described with continuous assignments or an always/process block sensitive to all inputs, describing a function with no memory. Sequential logic is described with an always @(posedge clk) block (or VHDL's clocked process), where every signal assigned inside becomes a flip-flop. A critical beginner mistake is an incomplete if/case in a combinational block: leaving out an else branch tells the synthesis tool to hold the previous value, which silently infers an unintended latch instead of pure combinational logic. Two coding styles map directly onto hardware: blocking assignments (=) model combinational logic evaluated in order, while non-blocking assignments (<=) model registers that all sample their inputs simultaneously and update together at the clock edge; mixing them incorrectly is a classic source of simulation/synthesis mismatches. Synthesis Synthesis translates a register-transfer level (RTL) description written in an HDL into a gate-level netlist built from the target technology's standard cells or, for an FPGA, from look-up tables (LUTs) and flip-flops. The synthesis tool infers flip-flops from clocked always-blocks, infers multiplexers from if/case statements, optimises Boolean logic (constant propagation, common sub-expression elimination, technology mapping), and maps the result onto the field-programmable gate array (FPGA)'s basic logic elements: typically a k-input LUT (which can implement any function of k inputs by acting as a tiny lookup table) paired with a flip-flop, replicated across the device as configurable logic blocks. Place and route Once synthesis produces a netlist of LUTs, flip-flops, and hard blocks (like RAMs or multipliers), place-and-route assigns each netlist element to a physical site on the FPGA fabric (placement) and configures the programmable interconnect switches to realise every net (routing), all while trying to meet the target clock frequency. Timing-driven place-and-route iterates: it estimates delays, identifies the critical path (the longest combinational path between two registers), and re-places or re-routes to shorten it. The output is a bitstream: the configuration data that, loaded into the FPGA, sets every LUT's truth table and every routing switch. Testbenches A testbench is HDL code that is never synthesised; it exists purely to drive stimulus into a design-under-test and check its responses in simulation. A typical self-checking testbench instantiates the design, generates a clock, applies a reset, drives input vectors (directed test cases plus, in more advanced flows, randomised ones), and compares outputs against expected values automatically, reporting pass/fail rather than requiring a human to read waveforms. Simulating in a testbench before touching real hardware catches the vast majority of logic bugs far faster and more cheaply than debugging on an FPGA, where internal signals are far harder to observe. Static timing analysis Static timing analysis (STA) checks every timing path in a synthesised netlist algebraically against the target clock period, without simulating any input vectors at all, which is what makes it exhaustive in a way that simulation-based verification cannot be: a design with millions of paths would need an impractical number of directed simulation runs to exercise every one, while STA evaluates them all in a single pass. STA reports the worst-case slack, the margin between a path's actual delay and the time budget the clock period allows, and any path with negative slack is a timing violation that must be fixed, whether by re-synthesising with different constraints, restructuring the logic, or accepting a lower clock frequency. Design reuse and IP cores Few designs are built entirely from scratch at the gate level; verified, pre-built blocks called intellectual property (IP) cores, ranging from a universal asynchronous receiver-transmitter (UART) to a full memory controller, are integrated as reusable units with a defined interface, saving the cost of re-verifying well-understood functionality. Reuse introduces its own risk, since an IP core's internal assumptions, such as a specific reset polarity or a fixed clock relationship, must match the system it is dropped into exactly, and a mismatch can silently corrupt behaviour despite each individual block passing its own testbench in isolation. This is why integrating a third-party IP core still requires system-level verification of the combined design, not just trust in the core's standalone test results. Related CCI capabilities Computer Architecture (Course): (https://www.cambridgecyberinternational.com/en/insights/academy/computer-architecture/). Optics Primer Series (Course): (https://www.cambridgecyberinternational.com/en/insights/academy/optics/). Maths Refresher Series, Finance (Course): (https://www.cambridgecyberinternational.com/en/insights/academy/maths-finance/). System Dynamics (Course): (https://www.cambridgecyberinternational.com/en/insights/academy/system-dynamics/). CCI Lab: Run it, build with it, read the thinking, reuse the data. (https://www.cambridgecyberinternational.com/en/insights/lab/)